This invention relates generally to methods for forming silicon-on-insulator (SOI) substrates, and more particularly, to methods for forming such substrates having internal sites for sequestering metallic impurities present in the substrate.
SOI wafers have become increasingly common starting substrates for generating a variety of semiconductor electronic devices. SOI wafers typically contain a device layer formed in a silicon substrate above a buried continuous silicon oxide layer that separates the device layer from the remainder of the substrate. The buried oxide layer can be generated, for example, by employing techniques generally known by the acronym SIMOX (Separation by Implantation of Oxygen). A variety of integrated circuits can be fabricated in the device layer. Such integrated circuits typically include thousands, or even millions, of devices, such as transistors or logic gates.
Silicon wafers, however, typically contain metallic impurities, such as, copper, nickel, iron, gold, chromium, or silver, among others. Trace amounts of such metallic impurities can be present in a silicon ingot from which the wafer is cut. Additionally, subsequent processing of the wafers in ion implanters, high temperature furnaces, or other wafer processing tools, employed during manufacturing of SOI wafers or in later IC processing of the wafers, can expose the wafers to metallic impurities that can originate from metallic components of these tools and/or from contaminants present in process gases and/or other chemicals.
At elevated temperatures that are routinely utilized in semiconductor IC fabrication, these metallic impurities can rapidly diffuse through the silicon substrate, and can be trapped in the device layer. Concentrations of such metallic impurities in the device layer beyond certain thresholds can adversely affect critical characteristics of semiconductor devices formed in this layer, such as, leakage current and breakdown voltage of p-n junctions, integrity of gate dielectric in MOS transistors and current gain in bipolar devices.
One method utilized in the art for lowering the concentration of metallic impurities in a wafer is to form a polycrystalline silicon layer on a back surface of the wafer. Such a polycrystalline layer functions as a precipitation region for the mobile metallic impurities. However, wafers formed with such polycrystalline layers, often referred to as “poly-back” wafers, have several limitations that make them undesirable to integrated circuit device manufacturers. For example, polycrystalline silicon surfaces are inherently rough and more likely to trap particulate contaminants from the processing environment during IC manufacturing. Further, the uneven topography of the polycrystalline layer renders measurement of particulate contamination on the poly-back layer impractical. When such wafers are stacked during processing, particles trapped by the polyback layer can also be shed to the front surfaces of adjacent wafers where active devices are formed. Many conventional wafer manufacturers, as well as some SOI wafer fabricators, have abandoned the polyback approach altogether in favor of “double-polished” wafers that include both a polished top surface as well as a polished back surface.
Another disadvantage of a poly-back wafer is that the rough surface topography of the polycrystalline surface can render precise positioning of the wafer for lithographical applications impractical.
The undesirable properties of polyback wafers thus require new approaches to achieving reduction of metallic contamination in the wafer device region, especially in SIMOX wafer manufacturing.
Hence, there is a need for enhanced methods for generating SOI wafers having low concentration of metallic impurities in the device layer.